The GAA channels are formed using epitaxy and selective materials removal, technologies that enable customers to precisely engineer the width and uniformity for optimum power and performance. GAA transistors resemble FinFET transistors that have been rotated by 90 degrees so that the channels are horizontal instead of vertical. The non-uniformity negatively impacts power and performance, which is one of the major reasons customers are moving to GAA. In FinFETs, the vertical channels that form the transistors electrical path are shaped by lithography and etch, processes that can result in uneven channel widths. Innovations in materials engineering provide GAA transistors with improvements in power and performance as well. The emerging GAA transistor exemplifies how customers can supplement 2D scaling with 3D design techniques and DTCO layout innovations to rapidly increase logic density even as 2D scaling slows. Applied nearly doubled its eBeam system revenue in 2021 and has become the number-one supplier of eBeam technology.Įngineering 3D Gate-All-Around Transistors
As a result, Applieds Sym3 technology is quickly growing beyond memory where Applied is the number-one supplier of conductor etch systems to the DRAM market to foundry-logic.Īpplied also demonstrated how its PROVision eBeam metrology technology can be used to see deeply within multilayer chips to precisely measure EUV-patterned features across the entire wafer, helping customers solve edge placement errors that other metrology techniques cannot diagnose. The improved EUV patterns increase yields and improve chip power and performance. The Sym3 chambers gently remove EUV resist materials and then redeposit material in a special way that averages out the pattern variability caused by stochastic errors.
Compared to spin-on deposition, Applieds CVD film helps customers tune the EUV hardmask layers for specific thicknesses and etch resiliency so they can achieve near-perfect EUV pattern transfer uniformity across the entire wafer.Īpplied also detailed a special capability of its Sym3 Y etch systems which enables customers to etch and deposit materials in the same chambers to help improve EUV patterns before they are etched into the wafer. Today, Applied is introducing the Stensar Advanced Patterning Film for EUV which is deposited using Applieds Precision CVD (chemical vapor deposition) system. Until now, these layers have been deposited using spin-on technology.
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However, the industry has reached a point where further scaling with EUV is introducing challenges that require new approaches to deposition, etch and metrology.įollowing EUV resist development, chip patterns need to be etched through a series of intermediate layers called the transfer layer and hardmask before they are finally etched into the wafer. The emergence of extreme ultraviolet (EUV) lithography has enabled chipmakers to produce smaller features and increase transistor density. We are also detailing how GAA transistors will be manufactured in fundamentally different ways than todays FinFET transistors, and how Applied is ready with the broadest product line for GAA manufacturing including new steps in epitaxy, atomic layer deposition and selective materials removal along with two new Integrated Materials Solutions TM for creating ideal GAA gate oxides and metal gates. Prabu Raja, Senior Vice President and General Manager of the Semiconductor Products Group at Applied Materials.
Together, these techniques can help chipmakers as they aim to deliver future generations of logic chips with improved power, performance, area, cost and time-to-market or PPACt.Īpplieds strategy is to be the PPACt enablement company for our customers, and today we are presenting seven innovations designed to enable customers to continue 2D scaling with EUV, said Dr. These latter approaches, which include backside power distribution networks and Gate-All-Around (GAA) transistors, are expected to drive a growing proportion of logic density improvements in future years as classic 2D scaling slows. The other is using design technology cooptimization (DTCO) and 3D techniques that cleverly optimize the layout of logic cells to increase density independent of changes in the lithography pitch. One is classic Moores Law 2D scaling, creating smaller features using EUV lithography and materials engineering. Chipmakers are pursuing two complementary paths to increase transistor density in the years ahead.
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